Superscalar processors are designed to issue more than one instruction per clock cycle. Generally these processors comprise one or more reservation stations that receive and store instructions until they are ready to be issued to the out-of-order pipelines for execution. An instruction is said to be ready for issue when all of its input operands are available.
Each clock cycle the reservation station selects a number of ready instructions (e.g. one per out-of-order pipeline) and issues them to the out-of-order pipelines for execution. However, in any given clock cycle there can be a number of instructions that are ready for issue. Accordingly, there must be some mechanism for selecting ready instructions to issue to the out-of-order pipelines.
Typically the highest priority is given to the oldest ready instructions and the lowest priority is given to the youngest ready instructions. Issuing the oldest instructions as soon as possible ensures that the re-order buffer does not fill up and stall the dispatching of instructions. However, this policy alone does not ensure optimum processor performance.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known processors.